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sine_wave_2011_0329
- 正弦波波形发生器，verilog编写，Modsim仿真。-sine wave genonter
xinhao
- 基于verilog的数字信号产生器，包括三角波、方波、正弦波，频率可调。-Verilog-based digital signal generator, including a triangle wave, square wave, sine wave, frequency adjustable.
DDS-frequency-synthesizer
- 本文主要讨论了Verilog语言的基于DDS的波形发生器的设计。从设计要求入手，本文给出了DDS的详细设计过程，包括各个模块的设计思想，电路图，Verilog语言程序代码。其大致思想为通过频率控制字和相位控制字去控制正弦函数的ROM存储表的地址并对应着得到其幅度值，最终达到输出需要波形的目的。-This paper mainly discusses the design of the Verilog language, the DDS-based waveform generator. Star
DDS-SIN
- 用verilog语言实现DDS的正弦波发送-DDS sine wave sent verilog language
sinw
- 用verilog写的正弦波发生器，QuartusⅡ环境-Sine wave generator written in Verilog
sin_generate
- verilog 实现 dds正弦 函数信号发生器 verilog 实现 dds正弦 函数信号发生器-verilog achieve dds sine function signal generator verilog verilog dds sine function signal generator the dds sine function signal generator
DDS
- DDS正弦波发生模块 基于verilog语言实现 在cycloneii系列FPGA上经过验证 频率步进1khz 共有256个点-The DDS sine wave module based on verilog language achieve in cycloneii series FPGA proven frequency stepping 1khz 256 points
verilog_dds
- verilog实现dds，用于FPGA产生正弦波，适用于Cyclone 2系列-verilog achieve dds, FPGA is used to generate the sine wave, in the Cyclone Series
dds_project
- DDS直接数字频率合成器，能产生正弦波，方波，锯齿波，三角波四种波形，同时能在12864上显示波形类型和频率，用FPGA verilog实现的-DDS direct digital frequency synthesizer can produce sine, square wave, sawtooth wave, triangle wave four waveform, while in the 12864 on display the waveform type and frequency
frequency
- 能够检测方波正弦波以及锯齿波的频率，并且以及试过可以运行，采用的开发环境是ISE，编程语言是Verilog-Able to detect a square wave frequency of the sine wave and sawtooth wave, and as well tried can run the development environment is the ISE, the programming language is Verilog
dds_mul
- 简单的多周期dds的verilog编程，出来一个正弦波，可任意改变频率字-Simple multi-cycle dds verilog programming, out of a sine wave, the frequency can be arbitrarily changed words
zhengxiansanjiao
- 用Verilog实现正弦波和三角波，验证过的，功能正确-Sine wave and triangular wave with Verilog and verified correct function
zhengxian
- verilog的正弦函数信号发生器的设计。可生成不同的正弦函数信号波形。-verilog sine function signal generator design. Can generate a different signal waveform of the sine function.
cordic_iterate
- it is a code for cordic algorithm in verilog. it computes sine and cosine of an angle which is the input. it is iterative structure of cordic.
5-17
- 用verilog实现一个基于流水线结构的正、余弦信号发生器-Based on Pipeline Structure verilog to achieve a sine and cosine signal generator
e
- 基于verilog语言编写的代码。功能：可实现三角波，正弦波，方波的测量。-Based on Verilog language code. : Triangle wave, sine wave, square wave measurement.
zhengxianbo
- 正弦波发生器，基于verilog语言编写的，不用用DAC模块，直接输出0和1电频，经过RC滤波后就可得到波形-Sine wave generator, based on verilog language, do not use the DAC module, direct output power frequency 0 and 1, RC-filtered waveform obtained after
FIFO
- 将ROM的正弦波数据输入FIFO存储器，然后输出，有modelsim仿真波形-Verilog FIFO ROM mif sine
sinwave
- 使用verilog hdl语言编程正弦波信号，能仿真出结果-Can use verilog HDL language programming sine wave signal, the simulation results
dds
- 在altera的FPGA上实现直接数字频率合成，即用verilog实现DDS，输出正弦波形，在modelsim软件中仿真通过，已包含所有代码和工程以及二进制流文件。-The realization of direct digital frequency synthesis in the Altera FPGA, which is implemented by Verilog DDS, the output sine wave, through the simulation in Modelsim